深圳·新普京888.3(娱乐)APP平台-智库百科 NO.1

• 32-bit low-power RISC core with highly optimized 3-stage pipeline

• Supporting byte, half-word, and word memory access

• Supporting interrupt nesting

• Supporting single-cycle 32-bit x 32-bit hardware integer multiplier array, 3 to13 cycle hardware integer frequency divider array

• Memory Protection Unit (MPU)

• Low power consumption and high performance

• Supporting Cache

• Timing module EPT

• 32 K bytes of SRAM

• 16K bytes of ROM

• 256K byte EFLASH

     - 512 bytes/page

     - minimum 100,000 erase cycles

• DMA/EDMA

• 2 timers (PIT)

• Watchdog (WDT)

• Time counter (TC)

• 1024bit RSA

• 2048bit RSA

• 256bit SM2 prime domain

• DES/3DES supports ECB/CBC mode

• AES supports ECB/CBC/CFB/OFB/CTR mode

• SM4 supports ECB/CBC/CFB/OFB modes

• SM3

• SHA-0/ SHA-1/ SHA-224/ SHA-256 

• Supporting CRC32/ CRC16/ CRC

• Supporting DMAC operation

• Application-oriented memory partitioning with hardware support for secure isolation

• Scrambling bus

• True  random number generator, compliant with FIPS 140-2 standards and national commercial cryptography standards

• Voltage detection unit

• Light detection unit

• Power supply burr detection unit

• Metal shielding protection

• Temperature detection unit

• Frequency detection unit

• Clock and reset pulse filtering

• Optimizing wire routing for security

• Unique serial number for each product

• Main power input voltage: 1.62V~5.5V

• Maximum power consumption: 50mA @ 60MHz, deep sleep mode less than 1uA

• ESD: 2KV

• Supporting internal power-on reset and external reset

• Operating temperature: Consumer grade 0~70℃, Industrial grade -40~85℃

• Level II of security chip for commercial crypto product certification

• EAL4+ of China Information Technology Security Evaluation Center